PIC18CXX2_13 Datasheet, PDF (202/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
BZ
Branch if Zero
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] BZ n
-128  n  127
if Zero bit is ’1’
(PC) + 2 + 2n  PC
None
1110 0000 nnnn nnnn
If the Zero bit is ’1’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Decode
Read literal
'n'
No
operation
No
operation
If No Jump:
Q1
Q2
Decode
Read literal
'n'
Q3
Process
Data
No
operation
Q3
Process
Data
Q4
Write to PC
No
operation
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Zero =
PC
=
If Zero

PC
=
BZ Jump
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
CALL
Subroutine Call
Syntax:
Operands:
Operation:
[ label ] CALL k [,s]
0  k  1048575
s [0,1]
(PC) + 4  TOS,
k  PC<20:1>,
if s = 1
(WREG)  WS,
(STATUS)  STATUSS,
(BSR)  BSRS
Status Affected: None
Encoding:
1st word (k<7:0>) 1110
2nd word(k<19:8>) ¹¹¹¹
110s k₇kkk
k₁₉kkk kkkk
kkkk₀
kkkk₈
Description:
Subroutine call of entire 2M byte
memory range. First, return
address (PC+ 4) is pushed onto the
return stack. If ’s’ = 1, the W,
STATUS and BSR registers are
also pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If 's' = 0, no update
occurs (default). Then the 20-bit
value ’k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Read literal
'k'<7:0>,
No
operation
Push PC to
stack
No
operation
Read literal
’k’<19:8>,
Write to PC
No
operation
Example:
HERE
CALL THERE,1
Before Instruction
PC = Address(HERE)
After Instruction
PC = Address(THERE)
TOS = Address (HERE + 4)
WS = WREG
BSRS= BSR
STATUSS = STATUS
DS39026D-page 202
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