PIC18CXX2_13 Datasheet, PDF (23/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
2.7 Effects of SLEEP Mode on the
On-chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP will increase the current
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Note:
OSC Mode
OSC1 Pin
OSC2 Pin
RC
Floating, external resistor should
At logic low
pull high
RCIO
Floating, external resistor should
pull high
Configured as PORTA, bit 6
ECIO
Floating
Configured as PORTA, bit 6
EC
Floating
At logic low
LP, XT, and HS
Feedback inverter disabled, at
quiescent voltage level
Feedback inverter disabled, at
quiescent voltage level
See Table 3-1, in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.
2.8 Power-up Delays
Power up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see the “RESET” section.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer, OST, intended to keep the
chip in RESET until the crystal oscillator is stable.
With the PLL enabled (HS/PLL oscillator mode), the
time-out sequence following a Power-on Reset is differ-
ent from other oscillator modes. The time-out sequence
is as follows: First, the PWRT time-out is invoked after
a POR time delay has expired. Then, the Oscillator
Start-up Timer (OST) is invoked. However, this is still
not a sufficient amount of time to allow the PLL to lock
at high frequencies. The PWRT timer is used to provide
an additional fixed 2ms (nominal) time-out to allow the
PLL ample time to lock to the incoming clock frequency.
 1999-2013 Microchip Technology Inc.
DS39026D-page 23