PIC18CXX2_13 Datasheet, PDF (46/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
TABLE 4-2: REGISTER FILE SUMMARY
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Details
on page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
37
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
37
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
37
STKPTR
STKFUL STKUNF
—
Return Stack Pointer
00-0 0000
38
PCLATU
—
—
—
Holding Register for PC<20:16>
---0 0000
39
PCLATH
Holding Register for PC<15:8>
0000 0000
39
PCL
TBLPTRU
PC Low Byte (PC<7:0>)
—
—
bit21⁽²⁾
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
0000 0000
39
---0 0000
57
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
57
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
57
TABLAT
Program Memory Table Latch
0000 0000
57
PRODH
Product Register High Byte
xxxx xxxx
61
PRODL
Product Register Low Byte
xxxx xxxx
61
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
65
INTCON2
RBPU INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
RBIP 1111 -1-1
66
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF 11-0 0-00
67
INDF0
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
N/A
50
POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
N/A
50
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)
N/A
50
PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)
N/A
50
PLUSW0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) -
N/A
50
value of FSR0 offset by value in WREG
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte ---- 0000
50
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
50
WREG
Working Register
xxxx xxxx
INDF1
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
N/A
50
POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)
N/A
50
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)
N/A
50
PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
N/A
50
PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) -
N/A
50
value of FSR1 offset by value in WREG
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte ---- 0000
50
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
50
BSR
—
—
—
—
Bank Select Register
---- 0000
49
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
N/A
50
POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
N/A
50
POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)
N/A
50
PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
N/A
50
PLUSW2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) -
N/A
50
value of FSR2 offset by value in WREG
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- 0000
50
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
50
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx
52
TMR0H
Timer0 Register High Byte
0000 0000
95
TMR0L
Timer0 Register Low Byte
xxxx xxxx
95
T0CON
TMR0ON T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0 1111 1111
93
OSCCON
—
—
—
—
—
—
—
SCS
---- ---0
20
LVDCON
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0 --00 0101
175
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
DS39026D-page 46
 1999-2013 Microchip Technology Inc.