PIC18CXX2_13 Datasheet, PDF (210/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
IORLW
Inclusive OR literal with WREG
Syntax:
[ label ] IORLW k
Operands:
0  k  255
Operation:
(WREG) .OR. k  WREG
Status Affected: N,Z
Encoding:
0000 1001 kkkk kkkk
Description:
The contents of WREG are OR’ed
with the eight-bit literal 'k'. The
result is placed in WREG.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
literal 'k'
Q3
Process
Data
Q4
Write to
WREG
Example:
IORLW
Before Instruction
WREG = 0x9A
After Instruction
WREG = 0xBF
0x35
IORWF
Inclusive OR WREG with f
Syntax:
Operands:
Operation:
[ label ] IORWF f [,d [,a]
0  f  255
d  [0,1]
a  [0,1]
(WREG) .OR. (f)  dest
Status Affected:
Encoding:
Description:
N,Z
0001 00da ffff ffff
Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register 'f'
Q3
Process
Data
Q4
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT = 0x13
WREG = 0x91
After Instruction
RESULT = 0x13
WREG = 0x93
DS39026D-page 210
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