PIC18CXX2_13 Datasheet, PDF (110/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
13.4 Compare Mode
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the TMR1
register pair value or the TMR3 register pair value.
When a match occurs, the RC2/CCP1 (RC1/CCP2) pin
is:
• driven High
• driven Low
• toggle output (High to Low or Low to High)
• remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit, CCP1IF (CCP2IF) is set.
13.4.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
13.4.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
13.4.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
13.4.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCPx resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will start an A/D conversion if the
A/D module is enabled.
Note:
The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
FIGURE 13-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1or Timer3, but not set Timer1 or Timer3 Interrupt Flag bit,
and set bit GO/DONE (ADCON0<2>)
which starts an A/D Conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
RC2/CCP1
pin
TRISC<2>
Output Enable
QS
R
Output
Logic
CCP1CON<3:0>
Mode Select
Match
CCPR1H CCPR1L
Comparator
T3CCP2
01
Special Event Trigger
TMR1H TMR1L
TMR3H TMR3L
Set Flag bit CCP2IF T3CCP1
T3CCP2
RC1/CCP2
pin
TRISC<1>
Output Enable
QS
R
Output
Logic
CCP2CON<3:0>
Mode Select
Match
01
Comparator
CCPR2H CCPR2L
DS39026D-page 110
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