PIC18CXX2_13 Datasheet, PDF (199/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
BRA
Unconditional Branch
Syntax:
[ label ] BRA n
Operands:
-1024  n  1023
Operation:
(PC) + 2 + 2n  PC
Status Affected: None
Encoding:
1101 0nnn nnnn nnnn
Description:
Add the 2’s complement number
’2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a two-
cycle instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Decode
Read literal
'n'
No
operation
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
PC
=
BRA Jump
address (HERE)
address (Jump)
BSF
Bit Set f
Syntax:
Operands:
Operation:
[ label ] BSF
0  f  255
0b7
a [0,1]
1  f<b>
f,b[,a]
Status Affected: None
Encoding:
1000 bbba ffff ffff
Description:
Bit 'b' in register 'f' is set. If ‘a’ is 0
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register 'f'
Q3
Process
Data
Q4
Write
register 'f'
Example:
BSF
Before Instruction
FLAG_REG=
After Instruction
FLAG_REG=
FLAG_REG, 7, 1
0x0A
0x8A
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DS39026D-page 199