PIC18CXX2_13 Datasheet, PDF (252/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
FIGURE 21-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
78
79
SDO
80
MSb
79
78
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
74
73
Note: Refer to Figure 21-4 for load conditions.
LSb IN
TABLE 21-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No.
Symbol
Characteristic
70
TssL2scH, SS to SCK or SCK input
TssL2scL
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
73A TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
75
TdoR
SDO data output rise time PIC18CXXX
PIC18LCXXX
76
TdoF
SDO data output fall time
78
TscR
SCK output rise time
(Master mode)
PIC18CXXX
PIC18LCXXX
79
TscF
SCK output fall time (Master mode)
80
TscH2doV, SDO data output valid after PIC18CXXX
TscL2doV SCK edge
PIC18LCXXX
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
Min
Max Units Conditions
TCY
— ns
1.25TCY + 30 — ns
40
— ns
1.25TCY + 30 — ns
40
— ns
100
— ns
1.5TCY + 40 — ns
(Note 1)
(Note 1)
(Note 2)
100
— ns
—
25 ns
—
45 ns
—
25 ns
—
25 ns
—
45 ns
—
25 ns
—
50 ns
—
100 ns
DS39026D-page 252
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