PIC18CXX2_13 Datasheet, PDF (22/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
If the main oscillator is configured for HS-PLL mode, an
oscillator start-up time (TOST) plus an additional PLL
time-out (TPLL) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram, indicating the transition
from the Timer1 oscillator to the main oscillator for
HS-PLL mode, is shown in Figure 2-10.
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q4
Q1
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI
OSC1
OSC2
TOST
TPLL
PLL Clock
Input
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter PC
Note 1: TOST = 1024TOSC (drawing not to scale).
TOSC
1
TSCS
234 5678
PC + 2
PC + 4
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indi-
cating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-11.
FIGURE 2-11:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
Q1
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI
OSC1
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
TOSC
12 34 5 6 7 8
TSCS
Program Counter
PC
Note 1: RC oscillator mode assumed.
PC + 2
PC + 4
DS39026D-page 22
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