PIC18CXX2_13 Datasheet, PDF (205/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
CPFSGT
Compare f with WREG,
skip if f > WREG
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] CPFSGT f [,a]
0  f  255
a  [0,1]
(f) WREG),
skip if (f) > (WREG)
(unsigned comparison)
None
0110 010a ffff ffff
Compares the contents of data
memory location 'f' to the contents
of the WREG by performing an
unsigned subtraction.
If the contents of 'f' are greater than
the contents of WREG, then the
fetched instruction is discarded and
a NOP is executed instead, making
this a two-cycle instruction. If ‘a’ is
0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register 'f'
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC
=
WREG
=
After Instruction
Address (HERE)
?
If REG
PC
If REG
PC
> WREG;
= Address (GREATER)
 WREG;
= Address (NGREATER)
 1999-2013 Microchip Technology Inc.
CPFSLT
Compare f with WREG,
skip if f < WREG
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
[ label ] CPFSLT f [,a]
0  f  255
a  [0,1]
(f) –WREG),
skip if (f) < (WREG)
(unsigned comparison)
None
0110 000a ffff ffff
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
If the contents of 'f' are less than
the contents of WREG, then the
fetched instruction is discarded and
a NOP is executed instead, making
this a two-cycle instruction. If ‘a’ is
0, the Access Bank will be
selected. If ’a’ is 1, the BSR will not
be overridden (default).
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Before Instruction
PC
=
W
=
After Instruction
Address (HERE)
?
If REG
PC
If REG
PC
< WREG;
= Address (LESS)
 WREG;
= Address (NLESS)
DS39026D-page 205