PIC18CXX2_13 Datasheet, PDF (134/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
14.4.4 I²C MASTER MODE SUPPORT
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to the SSPBUF register initiating transmis-
sion of data/address.
4. Generate a STOP condition on SDA and SCL.
5. Configure the I²C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
Note:
The MSSP module, when configured in I²C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
FIGURE 14-13: MSSP BLOCK DIAGRAM (I²C MASTER MODE)
SDA
SDA in
Read
Internal
Data Bus
Write
SSPBUF
SSPSR
MSb
Shift
Clock
LSb
SSPM3:SSPM0
SSPADD<6:0>
Baud
Rate
Generator
START bit, STOP bit,
Acknowledge
Generate
SCL
SCL in
Bus Collision
START bit Detect
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
DS39026D-page 134
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