English
Language : 

PIC18CXX2_13 Datasheet, PDF (28/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D
◁
PIC18CXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU 242 442 252 452
TOSH 242 442 252 452
TOSL 242 442 252 452
STKPTR 242 442 252 452
PCLATU 242 442 252 452
PCLATH 242 442 252 452
PCL
242 442 252 452
TBLPTRU 242 442 252 452
TBLPTRH 242 442 252 452
TBLPTRL 242 442 252 452
TABLAT 242 442 252 452
PRODH 242 442 252 452
PRODL 242 442 252 452
INTCON 242 442 252 452
INTCON2 242 442 252 452
INTCON3 242 442 252 452
INDF0 242 442 252 452
POSTINC0 242 442 252 452
POSTDEC0 242 442 252 452
PREINC0 242 442 252 452
PLUSW0 242 442 252 452
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
N/A
N/A
N/A
N/A
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
N/A
N/A
N/A
N/A
N/A
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
N/A
N/A
N/A
N/A
N/A
FSR0H 242 442 252 452
---- 0000
---- 0000
---- uuuu
FSR0L 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1 242 442 252 452
N/A
N/A
N/A
POSTINC1 242 442 252 452
N/A
N/A
N/A
POSTDEC1 242 442 252 452
N/A
N/A
N/A
PREINC1 242 442 252 452
N/A
N/A
N/A
PLUSW1 242 442 252 452
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
DS39026D-page 28
 1999-2013 Microchip Technology Inc.
 ▷