PIC18CXX2_13 Datasheet, PDF (64/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
FIGURE 7-1:
INTERRUPT LOGIC
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF
TMR1IE
TMR1IP
XXXXIF
XXXXIE
XXXXIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Additional Peripheral Interrupts
IPE
IPEN
GIEL/PEIE
IPEN
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF
TMR1IE
TMR1IP
XXXXIF
XXXXIE
XXXXIP
Additional Peripheral Interrupts
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Wake-up if in SLEEP mode
Interrupt to CPU
Vector to location
0008h
GIEH/GIE
Interrupt to CPU
Vector to Location
0018h
GIEL\PEIE
DS39026D-page 64
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