PIC18CXX2_13 Datasheet, PDF (221/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Right f (no carry)
[ label ] RRNCF f [,d [,a]
0  f  255
d  [0,1]
a  [0,1]
(f<n>)  dest<n-1>,
(f<0>)  dest<7>
N,Z
0100 00da ffff ffff
The contents of register 'f' are
rotated one bit to the right. If 'd' is 0,
the result is placed in WREG. If 'd'
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, then
the bank will be selected as per the
BSR value (default).
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register 'f'
Q3
Process
Data
Q4
Write to
destination
Example 1:
RRNCF REG, 1, 0
Before Instruction
REG
= 1101 0111
After Instruction
REG
= 1110 1011
Example 2:
RRNCF REG, 0, 0
Before Instruction
WREG = ?
REG
= 1101 0111
After Instruction
WREG
REG
= 1110 1011
= 1101 0111
SETF
Set f
Syntax:
[label] SETF f [,a]
Operands:
0  f  255
a [0,1]
Operation:
FFh  f
Status Affected: None
Encoding:
0110 100a ffff ffff
Description:
The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register 'f'
Q3
Process
Data
Q4
Write
register 'f'
Example:
SETF
Before Instruction
REG
=
After Instruction
REG
=
REG,1
0x5A
0xFF
 1999-2013 Microchip Technology Inc.
DS39026D-page 221