PIC18CXX2_13 Datasheet, PDF (166/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
REGISTER 16-2: ADCON1 REGISTER
R/W-0
R/W-0
U-0
ADFM ADCS2
—
bit 7
U-0
R/W-0 R/W-0 R/W-0 R/W-0
—
PCFG3 PCFG2 PCFG1 PCFG0
bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
ADCON1
ADCON0
<ADCS2> <ADCS1:ADCS0>
Clock Conversion
0
00
FOSC/2
0
01
FOSC/8
0
10
FOSC/32
0
11
FRC (clock derived from the internal A/D RC oscillator)
1
00
FOSC/4
1
01
FOSC/16
1
10
FOSC/64
1
11
FRC (clock derived from the internal A/D RC oscillator)
bit 5-4 Unimplemented: Read as '0'
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ VREF- C / R
0000 A A A A
A
A
A
A VDD VSS 8 / 0
0001 A
A
A
A VREF+ A
A
A AN3 VSS 7 / 1
0010 D D D A
A
A
A
A VDD VSS 5 / 0
0011 D
D
D
A VREF+ A
A
A AN3 VSS 4 / 1
0100 D D D D
A
D
A
A VDD VSS 3 / 0
0101 D
D
D
D VREF+ D
A
A AN3 VSS 2 / 1
011x D D D D
D
D
DD
—
— 0/0
1000 A
A
A
A VREF+ VREF- A
A AN3 AN2 6 / 2
1001 D D A A
A
A
A
A VDD VSS 6 / 0
1010 D
D
A
A VREF+ A
A
A AN3 VSS 5 / 1
1011 D
D
A
A VREF+ VREF- A
A AN3 AN2 4 / 2
1100 D
D
D
A VREF+ VREF- A
A AN3 AN2 3 / 2
1101 D
D
D
D VREF+ VREF- A
A AN3 AN2 2 / 2
1110 D D D D
D
D
D
A
VDD VSS 1 / 0
1111 D
D
D
D VREF+ VREF- D
A AN3 AN2 1 / 2
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx) are
forced to be an analog input.
DS39026D-page 166
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