PIC18CXX2_13 Datasheet, PDF (61/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
6.0 8 X 8 HARDWARE MULTIPLIER
6.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18CXX2 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 6-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 6-1: PERFORMANCE COMPARISON
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Multiply Method
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Program
Memory
(Words)
13
1
33
6
21
24
52
36
Cycles
(Max)
69
1
91
6
242
24
254
36
Time
@ 40 MHz
6.9 s
100 ns
9.1 s
600 ns
24.2 s
2.4 s
25.4 s
3.6 s
@ 10 MHz
27.6 s
400 ns
36.4 s
2.4 s
96.8 s
9.6 s
102.6 s
14.4 s
@ 4 MHz
69 s
1 s
91 s
6 s
242 s
24 s
254 s
36 s
6.2 Operation
Example 6-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 6-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 6-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
EXAMPLE 6-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
ARG1, W
ARG2
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Example 6-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 6-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 6-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 =
=
ARG1H:ARG1L  ARG2H:ARG2L
(ARG1H  ARG2H  2¹⁶)+
(ARG1H  ARG2L  2⁸)+
(ARG1L  ARG2H  2⁸)+
(ARG1L  ARG2L)
 1999-2013 Microchip Technology Inc.
DS39026D-page 61