PIC18CXX2_13 Datasheet, PDF (292/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
Code Examples
16 x 16 Signed Multiply Routine ................................ 62
16 x 16 Unsigned Multiply Routine ............................ 62
8 x 8 Signed Multiply Routine .................................... 61
8 x 8 Unsigned Multiply Routine ................................ 61
Changing Between Capture Prescalers ................... 109
Fast Register Stack .................................................... 39
Initializing PORTA ...................................................... 77
Initializing PORTB ...................................................... 80
Initializing PORTC ...................................................... 83
Initializing PORTD ...................................................... 85
Initializing PORTE ...................................................... 87
Loading the SSPBUF Register ................................ 122
Saving STATUS, WREG and BSR Registers
in RAM ............................................................... 75
Code Protection ....................................................... 179, 186
COMF ............................................................................... 204
Compare (CCP Module) ................................................... 110
Associated Registers ............................................... 111
Block Diagram .......................................................... 110
CCP Pin Configuration ............................................. 110
CCPR1H:CCPR1L Registers ................................... 110
Software Interrupt .................................................... 110
Special Event Trigger ......................... 99, 105, 110, 171
Timer1 Mode Selection ............................................ 110
Configuration Bits ............................................................. 179
Context Saving During Interrupts ....................................... 75
Example Code ........................................................... 75
Conversion Considerations .............................................. 288
CPFSEQ .......................................................................... 204
CPFSGT ........................................................................... 205
CPFSLT ........................................................................... 205
D
Data Memory ...................................................................... 42
General Purpose Registers ........................................ 42
Special Function Registers ........................................ 42
DAW ................................................................................. 206
DC Characteristics ................................................... 237, 240
DECF ............................................................................... 206
DECFSNZ ........................................................................ 207
DECFSZ ........................................................................... 207
Device Differences ........................................................... 287
Direct Addressing ............................................................... 51
E
Electrical Characteristics .................................................. 235
Errata ................................................................................... 5
F
Firmware Instructions ....................................................... 187
G
General Call Address Sequence ...................................... 133
General Call Address Support ......................................... 133
GOTO ............................................................................... 208
I
I/O Ports ............................................................................. 77
I²C (SSP Module) ............................................................ 128
ACK Pulse ....................................................... 128, 129
Addressing ............................................................... 129
Block Diagram ......................................................... 128
Read/Write Bit Information (R/W Bit) ....................... 129
Reception ................................................................ 129
Serial Clock (RC3/SCK/SCL) ................................... 129
Slave Mode .............................................................. 128
Timing Diagram, Data .............................................. 257
Timing Diagram, START/STOP Bits ........................ 256
Transmission ........................................................... 129
I²C Master Mode Reception ............................................ 139
I²C Master Mode Repeated START Condition ................ 138
I²C Module
Acknowledge Sequence Timing .............................. 142
Baud Rate Generator
Block Diagram
Baud Rate Generator ...................................... 136
BRG Reset Due to SDA Collision ............................ 146
BRG Timing ............................................................. 136
Bus Collision
Acknowledge ................................................... 144
Repeated START Condition ............................ 147
Repeated START Condition Timing
(Case 1) ................................................... 147
Repeated START Condition Timing
(Case 2) ................................................... 147
START Condition ............................................. 145
START Condition Timing ......................... 145, 146
STOP Condition ............................................... 148
STOP Condition Timing (Case 1) .................... 148
STOP Condition Timing (Case 2) .................... 148
Transmit Timing ............................................... 144
Bus Collision Timing ................................................ 144
Clock Arbitration ...................................................... 143
Clock Arbitration Timing (Master Transmit) ............. 143
General Call Address Support ................................. 133
Master Mode 7-bit Reception Timing ....................... 141
Master Mode Operation ........................................... 135
Master Mode START Condition ............................... 137
Master Mode Transmission ..................................... 139
Master Mode Transmit Sequence ............................ 135
Multi-Master Mode ................................................... 144
Repeat START Condition Timing ............................ 138
STOP Condition Receive or Transmit Timing .......... 143
STOP Condition Timing ........................................... 142
Waveforms for 7-bit Reception ................................ 130
Waveforms for 7-bit Transmission ........................... 130
ICEPIC In-Circuit Emulator .............................................. 230
ID Locations ............................................................. 179, 186
INCF ................................................................................ 208
INCFSZ ............................................................................ 209
In-Circuit Serial Programming (ICSP) ...................... 179, 186
Indirect Addressing ............................................................ 51
FSR Register ............................................................. 50
INFSNZ ............................................................................ 209
Instruction Cycle ................................................................ 39
Instruction Flow/Pipelining ................................................. 40
Instruction Format ............................................................ 189
DS39026D-page 292
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