PIC18CXX2_13 Datasheet, PDF (246/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
21.3.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 21-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
CLKOUT
1
3
3
4
4
2
TABLE 21-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Param. No. Symbol
Characteristic
Min
Max Units
Conditions
1A
FOSC External CLKIN
Frequency⁽¹⁾
DC
4
MHz XT osc
DC
25
MHz HS osc
4
10
MHz HS + PLL osc
DC
40
kHz LP osc
DC
40
MHz EC, ECIO
Oscillator Frequency⁽¹⁾
DC
4
MHz RC osc
0.1
4
MHz XT osc
4
25
MHz HS osc
4
10
MHz HS + PLL osc
5
200
kHz LP osc mode
1
TOSC External CLKIN Period⁽¹⁾
250
—
ns XT and RC osc
40
—
ns HS osc
100
250
ns HS + PLL osc
25
—
s LP osc
25
—
ns EC, ECIO
Oscillator Period⁽¹⁾
250
—
ns RC osc
250
10,000 ns XT osc
25
250
ns HS osc
100
250
ns HS + PLL osc
25
—
s LP osc
2
TCY
Instruction Cycle Time⁽¹⁾
100
—
ns TCY = 4/FOSC
3
TosL, External Clock in (OSC1)
30
—
ns XT osc
TosH High or Low Time
2.5
—
s LP osc
10
—
ns HS osc
4
TosR, External Clock in (OSC1)
—
20
ns XT osc
TosF Rise or Fall Time
—
50
ns LP osc
—
7.5
ns HS osc
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39026D-page 246
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