PIC18CXX2_13 Datasheet, PDF (121/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

14.3 SPI Mode
The SPI mode allows 8-bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) - RA5/SS/AN4
14.3.1 OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data input sample phase (middle or end of data
output time)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Figure 14-1 shows the block diagram of the MSSP
module, when in SPI mode.
PIC18CXX2
FIGURE 14-1:
Read
MSSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Write
SSPBUF reg
SDI
SDO
SSPSR reg
bit0
Shift
Clock
SS Control
Enable
SS
Edge
Select
SCK
2
Clock Select
SSPM3:SSPM0
SMP:CKE ₄
2
( ) TMR2 output
2
Edge
Select
Prescaler TOSC
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed
successfully.
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DS39026D-page 121