PIC18CXX2_13 Datasheet, PDF (30/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
ADRESH 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0 242 442 252 452
0000 0000
0000 0000
uuuu uuuu
ADCON1 242 442 252 452
--0- 0000
--0- 0000
--u- uuuu
CCPR1H 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON 242 442 252 452
--00 0000
--00 0000
--uu uuuu
CCPR2H 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON 242 442 252 452
--00 0000
--00 0000
--uu uuuu
TMR3H 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON 242 442 252 452
0000 0000
uuuu uuuu
uuuu uuuu
SPBRG 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
RCREG 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXREG 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXSTA 242 442 252 452
0000 -01x
0000 -01u
uuuu -uuu
RCSTA 242 442 252 452
0000 000x
0000 000u
uuuu uuuu
IPR2
PIR2
242 442 252 452
242 442 252 452
---- 1111
---- 0000
---- 1111
---- 0000
---- uuuu
---- uuuu⁽¹⁾
PIE2
242 442 252 452
---- 0000
---- 0000
---- uuuu
IPR1
242 442 252 452
1111 1111
1111 1111
uuuu uuuu
PIR1
242 442 252 452
242 442 252 452
242 442 252 452
-111 1111
0000 0000
-000 0000
-111 1111
0000 0000
-000 0000
-uuu uuuu
uuuu uuuu⁽¹⁾
-uuu uuuu⁽¹⁾
PIE1
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
242 442 252 452
-000 0000
-000 0000
-uuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
DS39026D-page 30
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