PIC18CXX2_13 Datasheet, PDF (296/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
S
SCI. See USART.
SCK .................................................................................. 121
SDI ................................................................................... 121
SDO ................................................................................. 121
Serial Clock, SCK ............................................................. 121
Serial Communication Interface. See USART
Serial Data In, SDI ........................................................... 121
Serial Data Out, SDO ....................................................... 121
Serial Peripheral Interface. See SPI
SETF ................................................................................ 221
Slave Select Synchronization ........................................... 125
Slave Select, SS .............................................................. 121
SLEEP .............................................................. 179, 185, 222
Software Simulator (MPLAB SIM) .................................... 230
Special Event Trigger. See Compare
Special Features of the CPU ............................................ 179
Configuration Registers ................................... 180–182
Special Function Registers ................................................ 42
Map ............................................................................ 45
SPI
Master Mode ............................................................ 124
Serial Clock .............................................................. 121
Serial Data In ........................................................... 121
Serial Data Out ........................................................ 121
Slave Select ............................................................. 121
SPI Clock ................................................................. 124
SPI Mode ................................................................. 121
SPI Master/Slave Connection .......................................... 123
SPI Module
Master/Slave Connection ......................................... 123
Slave Mode .............................................................. 125
Slave Select Synchronization .................................. 125
Slave Synch Timing ................................................. 125
Slave Timing with CKE = 0 ...................................... 126
Slave Timing with CKE = 1 ...................................... 126
SS .................................................................................... 121
SSP .................................................................................. 115
Block Diagram (SPI Mode) ...................................... 121
I²C Mode. See I²C.
SPI Mode ................................................................. 121
Associated Registers ....................................... 127
Block Diagram .................................................. 121
SPI Mode. See SPI.
SSPBUF ................................................................... 124
SSPCON1 ................................................................ 118
SSPCON2 Register ................................................. 120
SSPSR ..................................................................... 124
SSPSTAT ................................................................. 116
TMR2 Output for Clock Shift ............................ 101, 102
SSP Module
SPI Master Mode ..................................................... 124
SPI Master./Slave Connection ................................. 123
SPI Slave Mode ....................................................... 125
SSPCON1 Register .......................................................... 118
SSPOV ............................................................................. 139
SSPSTAT Register .......................................................... 116
R/W Bit ..................................................................... 129
STATUS Register ............................................................... 52
STKPTR Register ............................................................... 38
SUBFWB .......................................................................... 222
SUBLW ............................................................................ 223
SUBWF ............................................................................ 223
SUBWFB .......................................................................... 224
SWAPF ............................................................................ 224
Synchronous Serial Port. See SSP.
DS39026D-page 296
T
TABLAT Register ............................................................... 57
Table Pointer Operations (Table) ...................................... 57
Table Read Operation, Diagram ........................................ 55
Table Write Operation, Diagram ........................................ 55
TBLPTR Register ............................................................... 57
TBLRD ............................................................................. 225
TBLWT ............................................................................. 226
Timer0 ................................................................................ 93
Clock Source Edge Select (T0SE Bit) ....................... 95
Clock Source Select (T0CS Bit) ................................. 95
Overflow Interrupt ...................................................... 95
Prescaler. See Prescaler, Timer0
T0CON Register ........................................................ 93
Timing Diagram ....................................................... 249
Timer1 ................................................................................ 97
Block Diagram ........................................................... 98
Block Diagram (16-bit R/W Mode) ............................. 98
Oscillator .............................................. 97, 99, 103, 105
Overflow Interrupt ................................ 97, 99, 103, 105
Prescaler. .................................................................. 98
Special Event Trigger (CCP) ..................... 99, 105, 110
T1CON Register ........................................................ 97
Timing Diagram ....................................................... 249
TMR1H Register ................................................ 97, 103
TMR1L Register ................................................. 97, 103
Timer2 .............................................................................. 101
Associated Registers ............................................... 102
Block Diagram ......................................................... 102
Postscaler. See Postscaler, Timer2.
PR2 Register ................................................... 101, 112
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ............................................... 101, 102
T2CON Register ...................................................... 101
TMR2 Register ......................................................... 101
TMR2 to PR2 Match Interrupt .................. 101, 102, 112
Timer3 .............................................................................. 103
Associated Registers ............................................... 105
Block Diagram ......................................................... 104
Block Diagram (16-bit R/W Mode) ........................... 104
T3CON Register ...................................................... 103
Timing Diagrams
Acknowledge Sequence Timing .............................. 142
Baud Rate Generator with Clock Arbitration ............ 136
BRG Reset Due to SDA Collision ............................ 146
Bus Collision
START Condition Timing ................................. 145
Bus Collision During a Repeated START
Condition (Case 1) ........................................... 147
Bus Collision During a Repeated START
Condition (Case2) ............................................ 147
Bus Collision During a START Condition
(SCL = 0) ......................................................... 146
Bus Collision During a STOP Condition .................. 148
Bus Collision for Transmit and Acknowledge .......... 144
I²C Bus Data ............................................................ 259
I²C Master Mode First START Bit Timing ................ 137
I²C Master Mode Reception Timing ......................... 141
I²C Master Mode Transmission Timing ................... 140
Master Mode Transmit Clock Arbitration ................. 143
Repeat START Condition ........................................ 138
Slave Synchronization ............................................. 125
SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram ......................... 124
SPI Mode Timing (Slave Mode with CKE = 0) ......... 126
SPI Mode Timing (Slave Mode with CKE = 1) ......... 126
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