PIC18CXX2_13 Datasheet, PDF (104/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
12.1 Timer3 Operation
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer3 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 12.0).
FIGURE 12-1:
TIMER3 BLOCK DIAGRAM
TMR3IF
Overflow
Interrupt
Flag bit
TMR3H
CLR
TMR3L
CCP Special Trigger
T3CCPx
0
TMR3ON
On/Off
1
T3SYNC
Synchronized
Clock Input
T1OSO/
T13CKI
T1OSI
T1OSC
(3)
T1OSCEN _FOSC/4
Enable
Oscillator⁽¹⁾
Internal
Clock
1
Prescaler
1, 2, 4, 8
0
2
TMR3CS
T3CKPS1:T3CKPS0
Synchronize
det
SLEEP Input
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
Set TMR3IF Flag bit
on Overflow
8
TMR3
Timer3
High Byte
CLR
TMR3L
T1OSO/
T13CKI
T1OSI
To Timer1 Clock Input
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
CCP Special Trigger
T3CCPx
0
Synchronized
Clock Input
TMR3ON
On/Off
1
T3SYNC
FOSC/4
Internal
Clock
1
Prescaler
1, 2, 4, 8
0
2
T3CKPS1:T3CKPS0
TMR3CS
Synchronize
det
SLEEP Input
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39026D-page 104
 1999-2013 Microchip Technology Inc.