PIC18CXX2_13 Datasheet, PDF (218/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
RETFIE
Return from Interrupt
Syntax:
Operands:
Operation:
Status Affected:
[ label ] RETFIE [s]
s  [0,1]
(TOS)  PC,
1  GIE/GIEH or PEIE/GIEL,
if s = 1
(WS)  WREG,
(STATUSS)  STATUS,
(BSRS)  BSR,
PCLATU, PCLATH are unchanged.
GIE/GIEH,PEIE/GIEL.
Encoding:
Description:
Words:
0000 0000 0001 000s
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
WREG, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Decode
No
operation
No
operation
No
operation
Q3
No
operation
No
operation
Q4
pop PC from
stack
Set GIEH or
GIEL
No
operation
Example:
RETFIE 1
After Interrupt
PC
=
W
=
BSR
=
STATUS
=
GIE/GIEH, PEIE/GIEL=
TOS
WS
BSRS
STATUSS
1
RETLW
Return Literal to WREG
Syntax:
Operands:
Operation:
[ label ] RETLW k
0  k  255
k  WREG,
(TOS)  PC,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding:
0000 1100 kkkk kkkk
Description:
WREG is loaded with the eight-bit
literal 'k'. The program counter is
loaded from the top of the stack
(the return address). The high
address latch (PCLATH) remains
unchanged.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Read
literal 'k'
No
operation
Process
Data
No
operation
pop PC from
stack, Write
to WREG
No
operation
Example:
CALL TABLE
:
TABLE
ADDWF PCL
RETLW k0
RETLW k1
:
:
RETLW kn
; WREG contains table
; offset value
; WREG now has
; table value
; WREG = offset
; Begin table
;
; End of table
Before Instruction
WREG = 0x07
After Instruction
WREG = value of kn
DS39026D-page 218
 1999-2013 Microchip Technology Inc.