PIC18CXX2_13 Datasheet, PDF (214/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
MULLW
Multiply Literal with WREG
Syntax:
[ label ] MULLW k
Operands:
0  k  255
Operation:
(WREG) x k  PRODH:PRODL
Status Affected: None
Encoding:
0000 1101 kkkk kkkk
Description:
An unsigned multiplication is car-
ried out between the contents of
WREG and the 8-bit literal 'k'.
The 16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
WREG is unchanged.
None of the status flags are
affected.
Note that neither overflow, nor
carry is possible in this opera-
tion. A zero result is possible but
not detected.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULLW 0xC4
Before Instruction
WREG
=
PRODH
=
PRODL
=
After Instruction
0xE2
?
?
WREG
PRODH
PRODL
= 0xE2
= 0xAD
= 0x08
MULWF
Multiply WREG with f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
[ label ] MULWF f [,a]
0  f  255
a  [0,1]
(WREG) x (f)  PRODH:PRODL
None
0000 001a ffff ffff
An unsigned multiplication is car-
ried out between the contents of
WREG and the register file loca-
tion 'f'. The 16-bit result is stored
in the PRODH:PRODL register
pair. PRODH contains the high
byte.
Both WREG and 'f' are
unchanged.
None of the status flags are
affected.
Note that neither overflow, nor
carry is possible in this opera-
tion. A zero result is possible but
not detected. If ‘a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ‘a’=
1, then the bank will be selected
as per the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register 'f'
Q3
Process
Data
Q4
Write
registers
PRODH:
PRODL
Example:
MULWF REG, 1
Before Instruction
WREG
=
REG
=
PRODH
=
PRODL
=
After Instruction
0xC4
0xB5
?
?
WREG
REG
PRODH
PRODL
= 0xC4
= 0xB5
= 0x8A
= 0x94
DS39026D-page 214
 1999-2013 Microchip Technology Inc.