PIC18CXX2_13 Datasheet, PDF (255/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
FIGURE 21-15:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
77
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS to SCK or SCK input
TssL2scL
TCY
— ns
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25TCY + 30 — ns
40
— ns
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25TCY + 30 — ns
40
— ns
73A TB2B
Last clock edge of Byte1 to the first clock edge of Byte2 1.5TCY + 40 — ns
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
— ns
75
TdoR
SDO data output rise time
PIC18CXXX
—
25 ns
PIC18LCXXX
45 ns
76
TdoF
SDO data output fall time
—
25 ns
77
TssH2doZ SS to SDO output hi-impedance
10
50 ns
78
TscR
SCK output rise time
(Master mode)
PIC18CXXX
PIC18LCXXX
—
25 ns
—
45 ns
79
TscF
SCK output fall time (Master mode)
—
25 ns
80
TscH2doV, SDO data output valid after SCK PIC18CXXX
TscL2doV edge
PIC18LCXXX
—
50 ns
—
100 ns
82
TssL2doV SDO data output valid after SS PIC18CXXX
edge
PIC18LCXXX
—
50 ns
—
100 ns
83
TscH2ssH, SS  after SCK edge
TscL2ssH
1.5TCY + 40 ^{— ns}
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
(Note 1)
(Note 1)
(Note 2)
 1999-2013 Microchip Technology Inc.
DS39026D-page 255