PIC18CXX2_13 Datasheet, PDF (259/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
FIGURE 21-19: MASTER SSP I²C BUS DATA TIMING
SCL
SDA
In
SDA
Out
103
90
91
109
100
101
106
107
109
Note: Refer to Figure 21-4 for load conditions.
102
92
110
TABLE 21-18: MASTER SSP I²C BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100 THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
101 TLOW
Clock low time 100 kHz mode 2(TOSC)(BRG + 1) —
ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
102 TR
SDA and SCL 100 kHz mode
—
1000 ns CB is specified to be
rise time
400 kHz mode
20 + 0.1CB
300 ns from 10 to 400 pF
1 MHz mode⁽¹⁾
—
300 ns
103 TF
SDA and SCL 100 kHz mode
—
300 ns CB is specified to be
fall time
400 kHz mode
20 + 0.1CB
300 ns from 10 to 400 pF
1 MHz mode⁽¹⁾
—
100 ns
90
TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for
setup time
400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated START
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms ^condition
91
THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period the
hold time
400 kHz mode 2(TOSC)(BRG + 1) — ms first clock pulse is
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms ^generated
106 THD:DAT Data input
100 kHz mode
0
—
ns
hold time
400 kHz mode
0
0.9 ms
1 MHz mode⁽¹⁾
TBD
—
ns
107 TSU:DAT Data input
100 kHz mode
250
—
ns (Note 2)
setup time
400 kHz mode
100
—
ns
1 MHz mode⁽¹⁾
TBD
—
ns
92
TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) —
ms
setup time
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
109 TAA
Output valid from 100 kHz mode
—
3500 ns
clock
400 kHz mode
—
1000 ns
1 MHz mode⁽¹⁾
—
—
ns
110 TBUF
Bus free time 100 kHz mode
4.7
— ms Time the bus must be
400 kHz mode
1.3
— ms free before a new
1 MHz mode⁽¹⁾
TBD
— ms ^{transmission can start}
D102 CB
Bus capacitive loading
—
400 pF
Note 1: Maximum pin capacitance = 10 pF for all I²C pins.
2: A fast mode I²C bus device can be used in a standard mode I²C bus system, but parameter #107  250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to
the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL
line is released.
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DS39026D-page 259