PIC18CXX2_13 Datasheet, PDF (219/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
RETURN
Return from Subroutine
Syntax:
[ label ] RETURN [s]
Operands:
s  [0,1]
Operation:
(TOS)  PC,
if s = 1
(WS)  WREG,
(STATUSS)  STATUS,
(BSRS)  BSR,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding:
0000 0000 0001 001s
Description:
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’= 1, the contents of the
shadow registers WS, STATUSS
and BSRS are loaded into their cor-
responding registers, WREG,
STATUS and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Decode
No
operation
No
operation
No
operation
Q3
Process
Data
No
operation
Q4
pop PC from
stack
No
operation
Example:
RETURN
After Interrupt
PC = TOS
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Left f through Carry
[ label ] RLCF f [,d [,a]
0  f  255
d  [0,1]
a  [0,1]
(f<n>)  dest<n+1>,
(f<7>)  C,
(C)  dest<0>
C,N,Z
0011 01da ffff ffff
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
C
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register 'f'
Q3
Process
Data
Q4
Write to
destination
Example:
RLCF
REG, 0, 0
Before Instruction
REG
= 1110 0110
C
=0
After Instruction
REG
= 1110 0110
WREG = 1100 1100
C
=1
 1999-2013 Microchip Technology Inc.
DS39026D-page 219