PIC18CXX2_13 Datasheet, PDF(163/304 Page) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

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PIC18CXX2_13 Datasheet, PDF (163/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

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PIC18CXX2

15.4.2 USART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the SLEEP

mode and bit SREN, which is a âdon't careâ in Slave

mode.

If receive is enabled by setting bit CREN prior to the

SLEEP instruction, then a word may be received during

SLEEP. On completely receiving the word, the RSR

register will transfer the data to the RCREG register,

and if enable bit RCIE bit is set, the interrupt generated

will wake the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt vector.

To set up a Synchronous Slave Reception:

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

2. If interrupts are desired, set enable bit RCIE.

3. If 9-bit reception is desired, set bit RX9.

4. To enable reception, set enable bit CREN.

5. Flag bit RCIF will be set when reception is com-

plete. An interrupt will be generated if enable bit

RCIE was set.

6. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

7. Read the 8-bit received data by reading the

RCREG register.

8. If any error occurred, clear the error by clearing

bit CREN.

TABLE 15-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS

INTCON

PIR1

PIE1

IPR1

GIE/

GIEH

PSPIF(1)

PSPIE(1)

PSPIP(1)

PEIE/

GIEL

ADIF

ADIE

ADIP

TMR0IE INT0IE

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x

RCREG USART Receive Register

0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC â BRGH TRMT TX9D 0000 -010 0000 -010

SPBRG Baud Rate Generator Register

0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as '0'.

Shaded cells are not used for Synchronous Slave Reception.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits

clear.

ï£ 1999-2013 Microchip Technology Inc.

DS39026D-page 163

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