PIC18CXX2_13 Datasheet, PDF (247/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
TABLE 21-5: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V)
Param
No.
Symbol
Characteristic
TRC
CLK
PLL Start-up Time (Lock Time)
CLKOUT Stability (Jitter) using PLL
Min
Max Units
—
2
ms
-2
+2
%
Conditions
FIGURE 21-6:
OSC1
CLKOUT AND I/O TIMING
Q4
Q1
10
Q2
Q3
11
CLKOUT
13
14
I/O Pin
(input)
17
I/O Pin
(output)
old value
20, 21
Note: Refer to Figure 21-4 for load conditions.
19
18
15
12
16
new value
TABLE 21-6: CLKOUT AND I/O TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max Units Conditions
10
TosH2ckL OSC1 to CLKOUT
—
75
200
ns
(1)
11
TosH2ckH OSC1 to CLKOUT
—
75
200
ns
(1)
12
TckR
CLKOUT rise time
—
35
100
ns
(1)
13
TckF
CLKOUT fall time
—
35
100
ns
(1)
14
TckL2ioV CLKOUT  to Port out valid
—
— 0.5TCY + 20 ns
(1)
15
TioV2ckH Port in valid before CLKOUT 
0.25TCY + 25 —
—
ns
(1)
16
TckH2ioI Port in hold after CLKOUT 
0
—
—
ns
(1)
17
TosH2ioV OSC1 (Q1 cycle) to Port out valid
—
50
150
ns
18
TosH2ioI OSC1 (Q2 cycle) to PIC18CXXX
100
—
—
ns
18A
Port input invalid
PIC18LCXXX
200
—
—
ns
(I/O in hold time)
19
TioV2osH Port input valid to OSC1
(I/O in setup time)
0
—
—
ns
20
TioR
Port output rise time PIC18CXXX
—
12
25
ns
20A
PIC18LCXXX
—
—
50
ns
21
TioF
Port output fall time PIC18CXXX
—
12
25
ns
21A
PIC18LCXXX
—
—
50
ns
22†† TINP
INT pin high or low time
TCY
—
—
ns
23†† TRBP
RB7:RB4 change INT high or low time
TCY
—
—
ns
24†† TRCP
RC7:RC4 change INT high or low time
20
ns
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
 1999-2013 Microchip Technology Inc.
DS39026D-page 247