MC68HC908JW32_09 Datasheet, PDF (97/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Functional Description
7.3.4 Baud Rate
The communication baud rate is controlled by the crystal frequency and the state of the PTB0 pin (when
IRQ1 is set to V_TST) upon entry into monitor mode. When PTB0 is high, the divide by ratio is 1024. If the
PTB0 pin is at logic 0 upon entry into monitor mode, the divide by ratio is 512.
If monitor mode was entered with V_DD on IRQ1, then the divide by ratio is set at 1024, regardless of PTB0.
This condition for monitor mode entry requires that the reset vector is blank.
Table 7-3 lists external frequencies required to achieve a standard baud rate of 9600 BPS. Other
standard baud rates can be accomplished using proportionally higher or lower frequency generators. If
using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module
can handle.
Table 7-3. Monitor Baud Rate Selection
External
Frequency
4.9152 MHz
9.8304 MHz
9.8304 MHz
IRQ1
V_TST
V_TST
V_DD
PTB0
0
1
X
Internal
Frequency
2.4576 MHz
2.4576 MHz
2.4576 MHz
Baud Rate
(BPS)
9600
9600
9600
7.3.5 Commands
The monitor ROM firmware uses these commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
NOTE
Wait one bit time after each echo before sending the next byte.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
97