MC68HC908JW32_09 Datasheet, PDF (209/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Break Module Registers
SBSW — Break Wait Bit
SBSW can be read within the break interrupt routine. The user can modify the return address on the
stack by subtracting 1 from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
18.5.4 SIM Break Flag Control Register
The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while
the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BCFE
R
R
R
R
R
R
R
Write:
Reset: 0
R
= Reserved
Figure 18-7. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
209