MC68HC908JW32_09 Datasheet, PDF (67/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

CGM Registers
5.5 CGM Registers
The following registers control and monitor operation of the CGM:
• PLL control register (PCTL) — (See 5.5.1 PLL Control Register.)
• PLL bandwidth control register (PBWC) — (See 5.5.2 PLL Bandwidth Control Register.)
• PLL multiplier select registers (PMSH and PMSL) — (See 5.5.3 PLL Multiplier Select Registers.)
• PLL VCO range select register (PMRS) — (See 5.5.4 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS) — (See 5.5.5 PLL Reference Divider Select
Register.)
5.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits.
Address:
Read:
Write:
Reset:
$1090
Bit 7
PLLIE
0
6
5
4
PLLF
PLLON
BCS
3
PRE1
2
PRE0
0
1
0
0
0
= Unimplemented
Figure 5-4. PLL Control Register (PCTL)
1
VPR1
0
Bit 0
VPR0
0
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting
the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as logic 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the
PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF
bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 5.3.8 Base Clock
Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
67