MC68HC908JW32_09 Datasheet, PDF (165/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

PS2 Clock Generator Control and Status Registers
PRE — Prescaler Selection
These bits select prescaler divider ratio. Reset clears this bit.
1 = Divide by 480 is selected
0 = Divide by 160 is selected
CSEL[1:0] — Clock Frequency Selection bits.
These bits selects the clock divider ratio to cater for different clock source frequency. Reset clears
these bits.
Table 12-1. CSEL[1:0] Divider Ratio
CSEL[1:0]
00
01
10
11
Divider Ratio
1
2
4
Not used
Table 12-2. Clock Selection Summary
BUS
Frequency
8-MHz
6-MHz
4-MHz
PRE
(Divider Raito)
160
480
160
CSEL[1:0]
(Divider Ratio)
4
1
2
Port Output
Frequency
12.5 kHz
12.5 kHz
12.5 kHz
NOTE
Glitches may occur when CSEL[1:0] and PRE value can be altered while
PS2EN is set.
PS2IEN — PS2 Interrupt Mask
This read/write bit enables the periodic PS2 interrupt. Reset clears this bit.
1 = PS2 interrupt is enabled
0 = PS2 interrupt is disabled
CLKEN — Clock Output Enable bit
This read/write bit enables the open drain clock output. Reset clears this bit.
1 = Open drain clock output is enabled
0 = Open drain clock output is disabled
PS2EN — PS2 Clock Generator Module Enable
This read/write bit enables the module clock source. Reset clears this bit.
1 = Module enabled
0 = Module disabled
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
165