MC68HC908JW32_09 Datasheet, PDF (173/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Port B
Address:
Read:
Write:
Reset:
$0005
Bit 7
6
5
4
3
2
1
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1
0
0
0
0
0
0
0
Figure 13-6. Data Direction Register D (DDRD)
Bit 0
DDRB0
0
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 13-7 shows the port B I/O circuit logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRBx
PTBx
PTBx
READ PTD ($0003)
Figure 13-7. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-3 summarizes the operation of the port B pins.
Table 13-3. Port B Pin Functions
DDRB
Bit
0
1
PTB Bit
X⁽¹⁾
X
I/O Pin Mode
Input, Hi-Z⁽²⁾
Output
Accesses
to DDRB
Read/Write
DDRB[7:0]
DDRB[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
Accesses to PTB
Read
Pin
PTB[7:0]
Write
PTB[7:0]⁽³⁾
PTB[7:0]
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
173