MC68HC908JW32_09 Datasheet, PDF (95/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Functional Description
7.3.1 Entering Monitor Mode
Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a POR and will allow communication at 9600 baud provided one of the following
sets of conditions is met:
1. IRQ = V_TST (PLL off):
– The external clock is 4.9152 MHz with PTC1 low
2. IRQ = V_TST (PLL off):
– The external clock is 9.8304 MHz with PTC1 high
If V_TST is applied to IRQ and PTC1 is low upon monitor mode entry (above condition set 1), the bus
frequency is a divide-by-two of the input clock. If PTC1 is high with V_TST applied to IRQ upon monitor
mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTC1 pin low when
entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if V_TST is applied
to IRQ. In this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input
directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at
maximum bus frequency.
Table 7-1. Monitor Mode Signal Requirements and Options
IRQ
External
RST PTA2 PTA1 PTA0 PTC1 _Clock(1)
Bus
Freq.
PLL
COP
Baud
Rate
Comment
X
GND
X
X
X
X
X
0
X
Disabled
0
No operation until
reset goes high
PTA1 and PTA2
V_DD
V_TST(2)
or
0
V_TST
1
1
voltages only
0
4.9152
MHz
2.4576
MHz
required if
OFF Disabled 9600 _{IRQ = VTST;}
PTC1 determines
frequency divider
PTA1 and PTA2
V_TST
V_DD
or
0
(2)
V_TST
1
1
voltages only
1
9.8304
MHz
2.4576
MHz
required if
OFF Disabled 9600 _{IRQ = VTST;}
PTC1 determines
frequency divider
V_DD
V_DD
or
or
X
X
X
X
X
GND V_TST
—
OFF Enabled — Enters user mode
1. External clock is derived by a 4.9152/9.8304 MHz off-chip oscillator
2. Monitor mode entry by IRQ = V_TST, a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscil-
lator circuit is bypassed.
The COP module is disabled in monitor mode as long as V_TST is applied to either IRQ or RST.
This condition states that as long as V_TST is maintained on the IRQ pin after entering monitor mode, or if
V_TST is applied to RST after the initial reset to get into monitor mode (when V_TST was applied to IRQ),
then the COP will be disabled. In the latter situation, after V_TST is applied to the RST pin, V_TST can be
removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
95