MC68HC908JW32_09 Datasheet, PDF (201/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Chapter 17
Low-Voltage Inhibit (LVI)
17.1 Introduction
This section describes the low-voltage inhibit (LVI) module. The LVI module monitors the voltage on the
V_DD pin, and can force a reset when V_DD voltage falls below V_TRIPF1.
17.2 Features
Features of the LVI module include:
• Independent voltage monitoring circuits for V_DD
• Independent LVI circuit disable for V_DD
• Programmable LVI reset
• Programmable stop mode operation
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
$FE0F
LVI Status Register
(LVISR)
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 17-1. LVI I/O Register Summary
17.3 Functional Description
Figure 17-2 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
contains independent bandgap reference circuit and comparator for monitoring the V_DD voltage. An LVI
reset performs a MCU internal reset and drives the RST pin low to provide low-voltage protection to
external peripheral devices.
LVISTOP, LVIPWRD, LVIRSTD are in the CONFIG1 register. See Chapter 3 Configuration Registers
(CONFIG) for details of the LVI configuration bits. Once an LVI reset occurs, the MCU remains in reset
until V_DD rises above V_TRIPR1 which causes the MCU to exit reset. The output of the comparator controls
the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
201