MC68HC908JW32_09 Datasheet, PDF (76/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
÷2
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM, OSC)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
RESET
PIN LOGIC
V_DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 6-1. SIM Block Diagram
INTERRUPT SOURCES
CPU INTERFACE
Addr.
Register Name
$FE00
Read:
SIM Break Status Register
(SBSR)
Write:
Reset:
Note: Writing a logic 0 clears SBSW.
$FE01
Read:
SIM Reset Status Register
(SRSR)
Write:
POR:
$FE03
Read:
SIM Break Flag Control
Register (SBFCR)
Write:
Reset:
Bit 7
R
0
POR
1
BCFE
0
6
5
R
R
0
0
PIN
COP
0
0
R
R
= Unimplemented
4
3
2
1
Bit 0
SBSW
R
R
R
R
NOTE
0
0
0
0
0
ILOP
ILAD
USB
LVI
0
0
0
0
0
0
R
R
R
R
R
R = Reserved
Figure 6-2. SIM I/O Register Summary
MC68HC908JW32 Data Sheet, Rev. 6
76
Freescale Semiconductor