MC68HC908JW32_09 Datasheet, PDF (114/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Timer Interface Module (TIM)
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
8.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
8.7 TIM During Break Interrupts
A break interrupt stops the TIM counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 6.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
8.8 I/O Signals
Port C shares three of its pins with the TIM. The two TIM channel I/O pins are PTC0/T1CH0 and
PTC2/T1CH1; and the external clock input is PTC1/TCLK1.
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
T1CH0 can be configured as buffered output compare or buffered PWM pins.
8.8.1 TIM Clock Pin (PTC1/TCLK1)
PTC1/TCLK1 is an external clock input that can be the clock source for the TIM counter instead of the
prescaled internal bus clock. Select the PTC1/TCLK1 input by writing logic 1’s to the three prescaler
select bits, PS[2:0]. (See 8.9.1 TIM Status and Control Register.) The minimum T2CLK pulse width,
TCLK1_LMIN or TCLK1_HMIN, is:
------------------1-------------------
bus frequency
+
t_SU
The maximum TCLK1 frequency is: bus frequency ÷ 2
8.9 I/O Registers
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC AND T2SC.
MC68HC908JW32 Data Sheet, Rev. 6
114
Freescale Semiconductor