MC68HC908JW32_09 Datasheet, PDF (207/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Low-Power Modes
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode.
When software does not change the break address and clears the BRKA
bit in the first break interrupt routine, the next break interrupt will not be
generated after exiting the interrupt routine even when the internal address
bus matches the value written in the break address registers.
18.3.3 TIMI and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
18.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_TST is present on the RST pin.
18.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
18.4.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if SBSW is set. (See Chapter 6 System Integration Module (SIM).) Clear
the BW bit by writing logic 0 to it.
18.5 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• SIM break status register (SBSR)
• SIM break flag control register (SBFCR)
18.5.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
Address: $FE0E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
BRKE BRKA
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-3. Break Status and Control Register (BRKSCR)
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
207