MC68HC908JW32_09 Datasheet, PDF (180/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Input/Output (I/O) Ports
PTE3 pin functions as an external interrupt when PTE3IE=1 in the IRQ option control register (IOCR)
and USBEN=0 in the USB address register (USB disabled). (See 14.7 IRQ Status and Control
Register.)
PTE2 pin also muxed with PS2 clock generator module. (See Chapter 12 PS2 Clock Generator
(PS2CLK).)
D– and D+ — USB Data Pins
D– and D+ are the differential data lines used by the USB module. (See Chapter 11 USB 2.0 FS
Module.)
When the USB module is enabled, PTE2/D+ and PTE3/D– function as USB data pins D– and D+.
When the USB module is disabled, PTE2/D+ and PTE3/D– function as open drain high current pins
for PS/2 clock and data use.
NOTE
PTE2/D+ pin has two programmable pullup resistors. One is used for PTE2
when the USB module is disable and another is used for D+ when the USB
module is enabled.
Data direction register E (DDRE) does not affect the data direction of port E
pins that are being used by the SPI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. (See Table 13-5 . Port C Pin Functions.)
SS, MISO, MOSI, and SPSCK — SPI Functional Pins
These are the chip select, master-input-slave-output, master-output-slave-input and clock pins for the
SPI module. The SPI enable bit, SPE, in the SPI control register, SPCR, enables these pins as the SPI
functional pins and overrides any control from port I/O logic. See Chapter 10 Serial Peripheral Interface
Module (SPI).
13.6.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to
a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
Address: $0009
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRE7
Write:
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 13-15. Data Direction Register E (DDRE)
DDRE[7:2] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE[7:2], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
MC68HC908JW32 Data Sheet, Rev. 6
180
Freescale Semiconductor