MC68HC908JW32_09 Datasheet, PDF (118/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Timer Interface Module (TIM)
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH0F
Write: 0
CH0IE
MS0B
MS0A
ELS0B ELS0A
TOV0 CH0MAX
Reset: 0
0
0
0
0
0
0
0
Figure 8-9. TIM Channel 0 Status and Control Register (TSC0)
Address: $0013
Bit 7
Read: CH1F
Write: 0
Reset: 0
6
5
0
CH1IE
0
0
= Unimplemented
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Figure 8-10. TIM Channel 1 Status and Control Register (TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x
status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore,
an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1
channel 0 and TIM2 channel 0 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation.
See Table 8-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
MC68HC908JW32 Data Sheet, Rev. 6
118
Freescale Semiconductor