MC68HC908JW32_09 Datasheet, PDF (175/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Port C
13.4.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to
a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0006
Bit 7
6
5
4
3
2
1
DDRC3 DDRC2 DDRC1
0
0
0
0
0
0
0
= Unimplemented
Figure 13-9. Data Direction Register C (DDRC)
Bit 0
DDRC0
0
DDRC[3:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears DDRC[3:0], configuring all port C pins
as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 3.
Figure 13-10 shows the port C I/O logic.
READ DDRC ($0007)
WRITE DDRC ($0007)
RESET
WRITE PTC ($0002)
DDRCx
PTCx
PTCx
READ PTC ($0002)
Figure 13-10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a
logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-5 summarizes the operation of the port C pins.
Table 13-5. Port C Pin Functions
DDRC
Bit
0
1
PTC Bit
X⁽¹⁾
X
I/O Pin Mode
Input, Hi-Z⁽²⁾
Output
Accesses to DDRC
Read/Write
DDRC[3:0]
DDRC[3:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
Accesses to PTC
Read
Write
Pin
PTC[3:0]⁽³⁾
PTC[3:0]
PTC[3:0]
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
175