MC68HC908JW32_09 Datasheet, PDF (59/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Functional Description
Addr.
Register Name
Bit 7
6
5
4
$1090
Read:
PLLF
PLL Control Register
(PTCL)
Write:
PLLIE
PLLON
BCS
Reset: 0
0
1
0
PLL Bandwidth Control ^Read: _AUTO
LOCK
ACQ
0
$1091
Register Write:
(PBWC) _Reset:
0
0
0
0
PLL Multiplier Select ^Read:
0
0
0
0
$1092
Register High Write:
(PMSH) _Reset:
0
0
0
0
Read:
$1093
PLL Multiplier Select Register
Low (PMSL)
Write:
Reset:
MUL7
0
MUL6
1
MUL5
0
MUL4
0
$1094
Read:
1095PLL VCO Range Select
Register (PMRS)
Write:
Reset:
VRS7
0
VRS6
1
VRS5
0
VRS4
0
Read: 0
0
0
0
$1095
PLL Reference Divider Select
Register (PMDS)
Write:
Reset: 0
0
0
0
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
3
PRE1
0
0
2
PRE0
0
0
1
VPR1
0
0
0
0
0
MUL11 MUL10 MUL9
0
0
0
MUL3
MUL2
MUL1
0
0
0
VRS3
VRS2
VRS1
0
0
0
RDS3
RDS2
RDS1
0
0
0
R = Reserved
Figure 5-2. CGM I/O Register Summary
Bit 0
VPR0
0
R
MUL8
0
MUL0
0
VRS0
0
RDS0
1
5.3.1 Oscillator Module
The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module.
CGMXCLK when selected, is driven to SIM module to generate the system bus clock. CGMRCLK is used
by the phase-lock-loop to provide a higher frequency system bus clock. The oscillator module also
provides the reference clock for the timebase module (TBM). See Chapter 9 Timebase Module (TBM) for
detailed description on TBM.
5.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
59