MC68HC908JW32_09 Datasheet, PDF (75/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Chapter 6
System Integration Module (SIM)
6.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all
MCU activities. A block diagram of the SIM is shown in Figure 6-1. Figure 6-2 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
Table 6-1 shows the internal signal names used in this section.
Table 6-1. Signal Name Conventions
Signal Name
ICLK
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Description
Internal RC oscillator clock
Selected oscillator clock from oscillator module
PLL VCO output and the divided PLL output
CGMVCLK-based or oscillator-based clock output from CGM module
(Bus clock = CGMOUT ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
75