MC68HC908JW32_09 Datasheet, PDF (82/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

System Integration Module (SIM)
option register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of
4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode. External crystal applications should use
the full stop recovery time, that is, with SSREC cleared.
6.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 6.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. (See 6.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
6.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
6.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 6-8 shows
interrupt entry timing, and Figure 6-9 shows interrupt recovery timing.
MODULE
INTERRUPT
I-BIT
IAB
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
IDB
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
R/W
MODULE
INTERRUPT
I-BIT
Figure 6-8. Interrupt Entry Timing
IAB
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
IDB
CCR
A
X PC – 1[15:8] PC – 1[7:0] OPCODE OPERAND
R/W
Figure 6-9. Interrupt Recovery Timing
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
MC68HC908JW32 Data Sheet, Rev. 6
82
Freescale Semiconductor