MC68HC908JW32_09 Datasheet, PDF (72/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Clock Generator Module (CGM)
VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not
frequency sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding
software performance or from exceeding stack limitations.
NOTE
Software can select the CGMVCLK divided by three as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software should
make sure the PLL is locked before setting the BCS bit.
5.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
5.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and
turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power.
Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is
immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from
wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost.
5.7.2 Stop Mode
If the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2 register) for the selected oscillator is
configured to disabled the oscillator in stop mode, then the STOP instruction disables the CGM (oscillator
and phase locked loop) and holds low all CGM outputs (CGMOUT, CGMVCLK, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by three driving CGMOUT,
the PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the
oscillator clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from
STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear.
If the oscillator stop mode enable bit is configured for continuous oscillator operation in stop mode, then
the phase locked loop is shut off but the CGMXCLK will continue to drive the SIM and other MCU
sub-systems.
5.7.3 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 6.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write the PLL control register during the break state without affecting
the PLLF bit.
MC68HC908JW32 Data Sheet, Rev. 6
72
Freescale Semiconductor