MC68HC908JW32_09 Datasheet, PDF (62/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Clock Generator Module (CGM)
The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
• Before entering tracking mode (ACQ = 1), software must wait a given time, t_ACQ (See 5.8
Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL
control register (PCTL).
• Software must wait a given time, t_AL, after entering tracking mode before selecting the PLL as the
clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
5.3.6 Programming the PLL
The following procedure shows how to program the PLL.
NOTE
The round function in the following equations means that the real number
should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f_BUSDES, or the desired VCO frequency, f_VCLKDES; and then
solve for the other.
The relationship between f_BUS and f_VCLK is governed by the equation:
× f_VCLK = 6 f_BUS
2. Choose a practical PLL reference frequency, f_RCLK, and the reference clock divider, R. Typically,
the reference is 4MHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f_RCLK/R. For stability and lock time reduction,
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, f_VCLK, and the reference frequency, f_RCLK, is
f_VCLK = ^2----P_R----N---(f_RCLK)
where N is the integer range multiplier, between 1 and 4095.
In cases where desired bus frequency has some tolerance, choose f_RCLK to a value determined
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See Chapter 19 Electrical
Specifications.
Choose the reference divider, R = 1.
When the tolerance on the bus frequency is tight, choose f_RCLK to an integer divisor of f_BUSDES,
and R = 1. If f_RCLK cannot meet this requirement, use the following equation to solve for R with
practical choices of f_RCLK, and choose the f_RCLK that gives the lowest R.
R
=
round
R_M
A
X
×
⎧⎛
⎨⎜
⎩⎝
f--_{V----fC--R--L--C-K--L-D--K--E----S- ⎠⎟⎞}
–
i
nte
ge
⎛
r⎜
⎝
f--_{V----fC--R--L--C-K--L-D--K--E----S- ⎠⎟⎞}
⎫
⎬
⎭
MC68HC908JW32 Data Sheet, Rev. 6
62
Freescale Semiconductor