MC68HC908JW32_09 Datasheet, PDF (89/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Low-Power Modes
6.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module output (CGMOUT) in stop mode, stopping the CPU and
peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles
down to 32. This is ideal for applications using canned oscillators that do not require long start-up times
from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 6-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
IAB STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 6-18. Stop Mode Entry Timing
CGMXCLK
INT/BREAK
IAB
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 6-19. Stop Mode Recovery from Interrupt
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
89