MC68HC908JW32_09 Datasheet, PDF (157/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

USB Module Registers
SUSPND — SUSPEND Detection Flag
This read/write bit is set when the module detects a suspend state on the USB bus or the bus is idle
for 3ms. The module will enter suspend mode when this bit is set. In order to reduce the power
consumption, user is recommended to stop the USB module clock by clearing the USBCLKEN bit in
USBCR register before putting the MCU in STOP mode. Writing zero to clear the bit. Writing one to
the bit has no effect. Reset clears this bit.
1 = SUSPEND state is detected
0 = No suspend state is detected
11.5.3 USB Status Interrupt Mask Register (USIMR)
Address:
Read:
Write:
Reset:
$0053
Bit 7
R
0
R
6
5
0
SETUPIE
EP0_STALL
0
0
= Reserved
4
SOFIE
0
3
CONFIG_
CHGIE
0
2
USBRE-
SETIE
0
1
RESUME-
FIE
0
Figure 11-5. USB Status Interrupt Mask Register
Bit 0
SUSP-
NDIE
0
EP0_STALL — Forced EP0 STALL Handshake Enable
This write only bit is used to provide protocol STALL to the control endpoint. Writing one to the bit
causes endpoint 0 to return STALL in response to any IN or OUT token issue by the USB host until
the next SETUP transaction. The bit can only be erased by module hardware, writing zero to the bit
has no effect. Reset also clears this bit.
1 = Send STALL handshake
0 = Do not response STALL handshaking
SETUPIE — SETUP Request Interrupt Mask
This read/write bit enables a CPU interrupt request when GET_DESCRIPTOR, SYNC_FRAME or
class/vendor specific request is received or SETUP flag of USB status register (USBSR) is set. Reset
clears this bit.
1 = CPU interrupt is enabled when SETUP flag in USBSR is set
0 = CPU interrupt is disabled when SETUP flag in USBSR is set
SOFIE — Start-of-frame Interrupt Mask
This read/write bit enables a CPU interrupt request when a start-of-frame signal is detected on the
USB bus or SOF flag of USB status register (USBSR) is set. Reset clears this bit.
1 = SOF interrupt is enabled
0 = SOF interrupt is disabled
CONFIG_CHGIE — Configuration Change Interrupt Mask
This read/write bit enables a CPU interrupt request when a configuration change from zero to one is
detected or CONFIG_CHG flag of USB status register (USBSR) is set. Reset clears this bit.
1 = CPU interrupt is enabled when CONFIG_CHG flag in USBSR is set
0 = CPU interrupt is disabled when CONFIG_CHG flag in USBSR is set
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
157