MC68HC908JW32_09 Datasheet, PDF (179/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Port E
Table 13-7 shows the priority table for PTE2/D+ pin.
Table 13-7. PTE2/D+ Priority Table
USB Module
Enable
(USBEN)
1
1
0
PS2 Clock
Generator
Enable
(PS2EN)
X
X
1
0
1
0
0
0
0
0
0
0
0
Data
Direction
Control
(DDRE2)
X
X
X
X
1
1
0
0
5k Pullup
Enable
(PTE2P)
X
X
1/0
0
X
1
X
1
USB D+
Pullup
Enable
(DPPULPEN)
1
0
0
1/0
1
0
1
0
Pin Function
D+ with pullup to VREF33.
D+ without pullup
PS2 Clock output (open-drain) with
optional 5k pullup to VDD
PS2 Clock output (open-drain) with
optional 1.2k pullup to VREG33
GPIO output (open-drain) with 1.2K
pullup to REG33V
GPIO output (open-drain) with 5k
pullup to VDD
GPIO input with 1.2K pullup to
REG33V
GPIO input with 5K pullup to VDD
Table 13-8 shows the priority table for PTE3/D– pin.
Table 13-8. PTE3/D– Priority Table
USB Module
Enable (USBEN)
1
0
0
0
PTE3 IRQ Enable
(PT3IE)
X
1
0
0
Data Direction
Control (DDRE3)
X
X
0
1
5K Pullup Enable
(PTE3P)
X
0/1
0/1
0/1
Pin Function
USB D– pin
GPIO input with associated interrupt
function and optional 5k pullup to VDD
GPIO input with optional 5k pullup to
VDD
GPIO output (open-drain) with optional
5k pullup to VDD
PTE[7:2] — Port E Data Bits
PTE[7:2] are read/write, software-programmable bits. Data direction of each port E pin is under the
control of the corresponding bit in data direction register E.
The PTE3 and PTE2 pullup enable bits, PTE3P and PTE2P, in the port option control register 2
(POCR2) enable 5kΩ pullups to VDD on PTE3 and PTE2 if the USB module is disabled. (See 13.7
Port Options.)
The PTE2 USB pullup enable bits, DPPULLEN, in the port option control register 2 (POCR2) enable
USB pullups to VREF33 on PTE2 for USB operation. Either of PTE2P or DPPULLEN bit can be
activated at the one time, DPPULLEN bit has higher priority, it will always override the setting of PTE2P
bit.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
179