MC68HC908JW32_09 Datasheet, PDF (93/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Chapter 7
Monitor Mode (MON)
7.1 Introduction
This section describes the monitor mode (MON). The monitor mode allows complete testing of the MCU
through a single-wire interface with a host computer.
7.2 Features
Features of the monitor mode include:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between monitor ROM and host computer
• Standard mark/space non-return-to-zero (NRZ) communication with host computer
• Execution of code in RAM or ROM
• ROM memory security feature⁽¹⁾
• 960 bytes monitor ROM code size ($FC00–$FDFF and $FE10–$FFCE)
• Standard monitor mode entry if high voltage, V_TST, is applied to IRQ
7.3 Functional Description
The monitor module receives and executes commands from a host computer. Figure 7-1 shows an
example circuit used to enter monitor mode and communicate with a host computer via a standard
RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
The monitor code allows enabling the PLL to generate the internal clock, provided the reset vector is
blank, when the device is being clocked by a low-frequency crystal. This entry method, which is enabled
when IRQ is held low out of reset, is intended to support serial communication/ programming at 9600
baud in monitor mode.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the ROM difficult for
unauthorized users.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
93